(1) Field of the Invention
The invention relates to a method of reducing leakage current in the fabrication of integrated circuits, and more particularly, to a method of reducing leakage current of ultra-thin gate oxide by a novel pre-oxidation cleaning sequence in the manufacture of integrated circuits.
(2) Description of the Prior Art
For deep sub-micron CMOS technology, gate oxide has been scaled down aggressively toward the direct tunnelling current region. The thickness of the silicon dioxide layer is projected to be around 15 to 20 Angstroms for the coming 0.13 .mu.m technology. For such ultra-thin gate oxide, leakage current will increase tremendously as compared to previous technologies. Accordingly, this will cause standby power consumption of devices to rise significantly, making products commercially unacceptable. The leakage current of ultra-thin gate oxides must be reduced.
U.S. Pat. No. 5,393,686 to Yeh et al discloses cleaning a gate oxide layer using ammonia and hydroxide fluid. U.S. Pat. No. 5,709,755 to Kuo et al teaches an APM rinse of the front and back sides of a wafer following CMP. U.S. Pat. No. 5,849,104 to Mohindra et al shows a multi-step cleaning process which can be used as a pre-gate oxide clean. U.S. Pat. No. 5,704,986 to Chen et al teaches a dry cleaning of a semiconductor substrate. U.S. Pat. No. 5,878,760 to Mohindra et al teaches a substrate cleaning process.